// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: ${module_instance_name}

  // Top level dut name (sv module).
  dut: ${module_instance_name}

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: ${instance_vlnv(f"lowrisc:dv:{module_instance_name}_sim:0.1")}

  // Testplan hjson file.
  testplan: "{self_dir}/../data/${module_instance_name}_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{self_dir}/../data/${module_instance_name}.hjson"


  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["${module_instance_name}_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: ${module_instance_name}_base_test
  uvm_test_seq: ${module_instance_name}_base_vseq

  // Add GPIO specific exclusion files.
  vcs_cov_excl_files: ["{self_dir}/cov/gpio_cov_excl.el"]

  // Enable cdc instrumentation.
  run_opts: ["+cdc_instrumentation_enabled=1"]

  // Add a second build mode to test the input synchronizers.
  // Note that since the scoreboard has a cycle accurate model
  // for GPIO without the synchronizers, the majority of the tests
  // is run in the default build mode without the CDC prims. The en_cdc_prims
  // build mode is used to run some additional smoke checks to ensure
  // that the input paths through the CDC prims are connected correctly.
  build_modes: [
    {
      name: en_cdc_prims
      build_opts: ["+define+GPIO_ASYNC_ON"]
    }
  ]

  en_cdc_prims_vcs_cov_cfg_file: "{default_vcs_cov_cfg_file}"
  en_cdc_prims_xcelium_cov_cfg_file: "{default_xcelium_cov_cfg_file}"

  // List of test specifications.
  tests: [
    {
      name: gpio_smoke
      uvm_test_seq: gpio_smoke_vseq
    }

    {
      name: gpio_smoke_no_pullup_pulldown
      uvm_test_seq: gpio_smoke_vseq
      run_opts: ["+no_pullup_pulldown=1"]
    }

% if num_inp_period_counters > 0:
    {
      name: gpio_inp_prd_cnt
      uvm_test_seq: gpio_inp_prd_cnt_vseq
    }

% endif
    {
      name: gpio_random_dout_din
      uvm_test_seq: gpio_random_dout_din_vseq
    }

    {
      name: gpio_random_dout_din_no_pullup_pulldown
      uvm_test_seq: gpio_random_dout_din_vseq
      run_opts: ["+no_pullup_pulldown=1"]
    }

    {
      name: gpio_dout_din_regs_random_rw
      uvm_test_seq: gpio_dout_din_regs_random_rw_vseq
    }

    {
      name: gpio_intr_rand_pgm
      uvm_test_seq: gpio_intr_rand_pgm_vseq
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_rand_intr_trigger
      uvm_test_seq: gpio_rand_intr_trigger_vseq
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_intr_with_filter_rand_intr_event
      uvm_test_seq: gpio_intr_with_filter_rand_intr_event_vseq
      run_opts: ["+en_scb=0", "+zero_delays=1", "+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_filter_stress
      uvm_test_seq: gpio_filter_stress_vseq
      run_opts: ["+en_scb=0", "+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_random_long_reg_writes_reg_reads
      uvm_test_seq: gpio_random_long_reg_writes_reg_reads_vseq
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_full_random
      uvm_test_seq: gpio_full_random_vseq
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_stress_all
      uvm_test_seq: gpio_stress_all_vseq
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_stress_all_with_rand_reset
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_csr_rw
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_same_csr_outstanding
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_csr_aliasing
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_csr_mem_rw_with_rand_reset
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    {
      name: gpio_tl_intg_err
      run_opts: ["+do_clear_all_interrupts=0"]
    }

    // Additional smoke checks for second build mode
    {
      name: gpio_smoke_en_cdc_prim
      uvm_test_seq: gpio_smoke_vseq
      build_mode: en_cdc_prims
    }

    {
      name: gpio_smoke_no_pullup_pulldown_en_cdc_prim
      uvm_test_seq: gpio_smoke_vseq
      build_mode: en_cdc_prims
      run_opts: ["+no_pullup_pulldown=1"]
    }
    {
      name: gpio_rand_straps
      uvm_test_seq: gpio_rand_straps_vseq
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["gpio_smoke", "gpio_smoke_en_cdc_prim"]
    }
  ]
}
